DLL circuit adapted to semiconductor device

ABSTRACT

A DLL circuit is designed to adjust the delay time and the duty applied to an input clock signal, thus producing a DLL clock signal. In a non-clocking state of the DLL clock signal in which pulses disappear temporarily, the DLL circuit stops updating the delay time and the duty of the DLL clock signal. That is, the DLL circuit is capable of preventing a phase difference between the input clock signal and the DLL clock signal from being erroneously detected in the non-clocking state of the DLL clock signal, thus preventing the delay time and the duty from being updated based on the erroneously detected phase difference. Thus, it is possible to reduce the number of cycles adapted to the delay-locked control and to thereby stabilize the operation of the DLL circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to delay-locked loop (DLL) circuitsadapted to semiconductor devices.

The present application claims priority on Japanese Patent ApplicationNo. 2008-129638, the content of which is incorporated herein byreference.

2. Description of the Related Art

Due to increasing high-speed processing of electronic systems recentlydeveloped, it is necessary to perform high-speed data transfer betweensemiconductor devices installed in electronic systems, whereinsemiconductor devices employ clock synchronization methods. Assemiconductor memory devices, synchronous dynamic random-access memories(SDRAM) have been conventionally used and further developed intodouble-data-rate (DDR) SDRAM, DDR2 SDRAM, and DDR3 SDRAM which operatein synchronization with leading/trailing edges of clock pulses.

In order to establish synchronization with clock pulses, delay-lockedloop (DLL) circuits have been used for synchronous dynamic random-accessmemories (SDRAM) so as to establish synchronization of timing betweeninternal clock pulses and external clock pulses.

FIG. 9 shows an example of a DLL circuit in which a clock signal CK andan inverse clock signal /CK (where a slash or bar “/” indicates logicalinversion) from an external device (not shown) are supplied to aninitial circuit 11 and are then subjected to duty adjustment and delayadjustment, thus producing a DLL clock signal.

Along a path A shown by dotted lines, the DLL clock signal is suppliedto a DQ replica circuit 15, from which a DQ replica output signal issupplied to a phase detection circuit 16 and subjected to phasecomparison with the clock signal CK and the inverse clock signal /CK.The phase comparison result is fed back to a delay control circuit 13.Based on the phase comparison result output from the phase detectioncircuit 16, the delay control circuit 13 outputs a delay signal to adelay circuit 12 so as to adjust a delay element of the delay circuit12.

Along a path B shown by dotted lines, the DLL clock signal is suppliedto a duty detection circuit 21 and subjected to detection as to whethera duty thereof is above or below 50%. The duty detection result is fedback to a duty control circuit 22. Based on the duty detection resultoutput from the duty detection circuit 21, the duty control circuit 22outputs a control signal (i.e. a duty signal) to a duty adjustmentcircuit 23. The duty adjustment circuit 23 adjusts the duty of a clocksignal output from the initial circuit 11 based on the clock signal CKand the inverse clock signal /CK in accordance with the duty signaloutput from the duty control circuit 22.

The delay circuit 12 performs delay adjustment so as to cancel outtiming skew between the DQ replica output signal and the clock signal CK(or the inverse clock signal /CK). In addition, the duty adjustmentcircuit 23 performs duty adjustment such that the duty of the DLL clocksignal becomes equal to or close to 50%.

The clock signal output from the initial circuit 11 is subjected to afrequency dividing process by a counter clock generation circuit 17,which thus outputs a counter clock signal to a DLL cycle counter 18.Based on the counter clock signal, the DLL cycle counter 18 generates anupdate clock signal for a prescribed duration, thus outputting it to thedelay control circuit 13 and the duty control circuit 22. The delaycontrol circuit 13 and the duty control circuit 22 update theiroperations in response to the update clock signal.

It is necessary for the DLL circuit of FIG. 9 to perform a delay-lockedcontrol for establishing synchronization between the internal clocksignal and the external clock signal by way of a delay adjustment andduty adjustment with a small number of cycles during a DLL reset period;hence, it is necessary to simultaneously perform the delay adjustmentand the duty adjustment. At a high input clock frequency, each pulsewidth of the input clock signal varies greatly due to delay adjustmentduring the locked-control operation, thus causing the DLL clock signalto disappear temporarily.

Since the phase detection circuit 16 and the duty detection circuit 21trigger their operations in response to the DLL clock signal, it is verydifficult to precisely detect the phase in the period in which the DLLclock signal disappears.

Repeating the phase detection and the duty detection in erroneousmanners increases the number of cycles adapted to the delay-lockedcontrol and disables the delay-clocked control pursuant to prescribedtechnical specifications which are determined in advance. This requiresmanufacturers to solve the above problem due to the temporarydisappearance of the DLL clock signal.

Various technologies for canceling out deviations of duties of clocksignals have been developed and disclosed in various documents such asPatent Document 1.

-   Patent Document 1: Japanese Unexamined Patent Application    Publication No. 2002-42469

Patent Document 1 teaches a clock generation circuit which cancels outdeviations of the duty of an output clock signal (causing some problemsin phase control) by additionally using a simple circuit, thus achievinghigh-precision phase control. Specifically, a variable delay circuit isfollowed by a clock duty adjustment circuit and is controlled in thedelay time thereof at the leading edge of a clock pulse, wherein theclock duty adjustment circuit performs adjustment at the trailing edgewhen the phase of the output clock signal at its leading edge matchesthe phase of a reference clock signal, thus identifying the duty of theoutput clock signal with the duty of the reference clock signal.

The present inventors have recognized that the clock generation circuitof Patent Document 1 is not designed to solve the above problemregarding the delay-locked control in which the DLL circuit fails toprecisely perform phase adjustment due to erroneous detection during thedisappearance period of the DLL clock signal, thus increasing the numberof cycles adapted to the delay-locked control.

Due to the execution of the delay-locked control with a small number ofcycles during the DLL reset period, it is necessary for the DLL circuitto simultaneously perform the delay adjustment and the duty adjustment.At a high input clock frequency, each pulse width of the input clocksignal varies greatly due to delay adjustment during the delay-lockedcontrol so as to cause the disappearance period of the DLL clock signal,which makes it very difficult to precisely perform the phase detectionand the duty detection.

In addition, repeating the phase detection and the duty detection inerroneous manners increases the number of cycles adapted to thedelay-locked control and disables the delay-locked control pursuant toprescribed technical specifications.

SUMMARY

The invention seeks to solve the above problem, or to improve upon theproblem at least in part.

The present invention is directed to a DLL circuit which generates andmonitors a DLL clock signal based on an input clock signal and whichprevents a delay time and a duty from being updated based on the phasedetection result and the duty detection result erroneously produced dueto disappearance of the DLL clock signal, thus executing thedelay-locked control with a small number of cycles in a stable manner.

In one embodiment, a DLL circuit for adjusting the phase of an inputclock signal is constituted of delay control circuit for producing adelay signal so as to control a delay time applied to the input clocksignal, a delay circuit for applying the delay time to the input clocksignal based on the delay signal, thus producing a DLL clock signal, anda DLL clock detection circuit for detecting either a clocking state or anon-clocking state with respect to the DLL clock signal, wherein the DLLclock detection circuit controls the delay control circuit to stopupdating the delay time in the delay circuit in the non-clocking stateof the DLL clock signal.

In another embodiment, a DLL circuit for adjusting the duty of an inputclock signal is constituted of a duty control circuit for producing aduty signal so as to control the duty of the input clock signal, a dutyadjustment circuit for adjusting the duty of the input clock signalbased on the duty signal, thus producing a DLL clock signal, and a DLLclock detection circuit for detecting either a clocking state or anon-clocking state with respect to the DLL clock signal, wherein the DLLclock detection circuit controls the duty control circuit to stopupdating the duty in the duty adjustment circuit in the non-clockingstate of the DLL clock signal.

In the above, it is possible to prevent a phase difference between theinput clock signal and the DLL clock signal from being erroneouslydetected in the non-clocking state of the DLL clock signal in whichpulses disappear temporarily, thus preventing the delay time and theduty from being updated based on the erroneously detected phasedifference. Thus, it is possible to reduce the number of cycles adaptedto the delay-locked control and to thereby stabilize the operation ofthe DLL circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing the constitution of a DLL circuitaccording to a first embodiment of the present invention;

FIG. 2 is a block diagram showing the constitution of a DLL circuitaccording to a second embodiment of the present invention;

FIG. 3 is a block diagram showing the constitution of a DLL circuitaccording to a third embodiment of the present invention;

FIG. 4 is a block diagram showing the constitution of a DLL clockdetection circuit shown in FIGS. 1 to 3;

FIG. 5A shows the waveform of a counter clock signal output from acounter clock generation circuit shown in FIGS. 1 to 3;

FIG. 5B shows the waveform of a DLL clock detection enable signal outputfrom a DLL cycle counter shown in FIGS. 1 to 3;

FIG. 5C shows the waveform of a fractional clock signal generated by theDLL cycle counter based on the counter clock signal of FIG. 5A;

FIG. 5D shows the waveform of a DLL clock signal output from a delaycircuit shown in FIGS. 1 and 3;

FIG. 5E shows the waveform of a DLL clock detection result produced by aDLL clock detection circuit shown in FIGS. 1 to 3 with respect to theDLL clock signal;

FIG. 5F shows the waveform of an update clock signal output from the DLLcycle counter;

FIG. 6A shows the waveform of the DLL clock detection enable signal in aclocking state of the DLL clock signal;

FIG. 6B shows the waveform of the DLL clock signal in the clockingstate;

FIG. 6C shows the waveform of the DLL clock detection result in theclocking state of the DLL clock signal;

FIG. 6D shows the waveform of an update enable/disable signal in theclocking state of the DLL clock signal;

FIG. 6E shows the waveform of the update clock signal in the clockingstate of the DLL clock signal;

FIG. 6F shows the waveform of the DLL clock detection enable signal in anon-clocking state of the DLL clock signal;

FIG. 6G shows the waveform of the DLL clock signal in the non-clockingstate of the DLL clock signal;

FIG. 6H shows the waveform of the DLL clock detection result in thenon-clocking state of the DLL clock signal;

FIG. 6I shows the waveform of the update enable/disable signal in thenon-clocking state of the DLL clock signal;

FIG. 6J shows the waveform of the update clock signal in thenon-clocking state of the DLL clock signal;

FIG. 7 is a circuit diagram showing the constitution of a delay controlcircuit shown in FIGS. 1 and 3;

FIG. 8A is a circuit diagram showing the constitution of a dutydetection circuit shown in FIGS. 2 and 3;

FIG. 8B shows a part of the waveform of the DLL clock signal whose dutyis greater than 50%;

FIG. 8C shows a part of the waveform of the DLL clock signal whose dutyis less than 50%; and

FIG. 9 is a block diagram showing the constitution of the foregoing DLLcircuit.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purposes.

1. First Embodiment

FIG. 1 shows a DLL circuit according to a first embodiment of thepresent invention, which is designed to perform the phase control only,wherein parts identical to those shown in FIG. 9 are designated by thesame reference numerals. The DLL circuit of FIG. 1 includes a DQ buffer14 whose output signal is synchronized with the clock signal CK and theinverse clock signal /CK by correcting a delay time.

In FIG. 1, the initial circuit 11 receives a differential input signalcorresponding to the clock signals CK and /CK, thus producing a clocksignal for the DLL circuit. The clock signal output from the initialcircuit 11 is supplied to the delay circuit 12 and the counter clockgeneration circuit 17.

The counter clock generation circuit 17 divides the frequency of theclock signal so as to generate and output a counter clock signal (seeFIG. 5A) to the DLL cycle counter 18.

The delay circuit 12 includes a plurality of delay elements, one ofwhich is selected to impart a prescribed delay time to the clock signalin response to a delay signal output from the delay control circuit 13.

The delay control circuit 13 determines the delay time based on thephase detection result output from the phase detection circuit 16, thusoutputting the delay signal to the delay circuit 12. The DQ buffer 14buffers a DLL clock signal output from the delay circuit 12, thusoutputting a DQ signal. The DQ replica circuit 15 is a replica (or areplication) of the DQ buffer 14; that is, it is a buffer circuit havingthe same PVT dependency (i.e. dependency of process, voltage, andtemperature) as the DQ buffer 14.

The phase detection circuit 16 performs phase comparison between the DQreplica output signal (output from the DQ replica circuit 15) and theclock signals CK and /CK, thus outputting a phase detection resultrepresenting a phase difference between them to the delay controlcircuit 13. The DLL cycle counter 18 counts the number of pulsesincluded in the counter clock signal so as to generate an update clocksignal (see FIG. 5F) for updating the duty/delay control.

The DLL circuit of FIG. 1 additionally includes a DLL clock detectioncircuit 31, which is activated upon reception of a DLL clock detectionenable signal output from the DLL cycle counter 18 and which makesdetermination as to whether or not the DLL clock signal is disappeared(or whether or not the DLL clock signal is placed in a clocking state),thus executing or stopping the duty/delay control.

In the DLL circuit of FIG. 1, the initial circuit 11 converts thedifferential input signal (corresponding the clock signals CK and /CK)into the clock signal, which is then output to the delay circuit 12. Thedelay circuit 12 adjusts the delay time of the clock signal output fromthe initial circuit 11 in accordance with the delay signal output fromthe delay control circuit 13, thus outputting the DLL clock signal tothe DQ buffer 14.

The DLL clock signal output from the delay circuit 12 is also suppliedto the DQ replica circuit 15 which has the same PVT dependency as the DQbuffer 14. Since the DQ replica circuit 15 serves as a buffer circuithaving the same PVT dependency as the DQ buffer 14, the DQ replicaoutput signal is output at the same timing as the DQ buffer 14outputting the DQ output signal. The DQ replica output signal issupplied to the phase detection circuit 16 and subjected to phasecomparison with the clock signals CK and /CK. The phase detection resultoutput from the phase detection circuit 16 is supplied to the delaycontrol circuit 13, so that the delay circuit 12 adjusts the delay timebased on the delay signal output from the delay control circuit 13.

The DLL clock detection circuit 31 receives the DLL clock detectionenable signal (output from the DLL cycle counter 18) and the DLL clocksignal (output from the delay circuit 12), wherein the DLL clockdetection circuit 31 is periodically activated by the DLL clockdetection enable signal. The period of the DLL clock detection enablesignal is identical to the update period for updating the delay time.

The DLL clock detection circuit 31 makes determination as to whether ornot the DLL clock signal is placed in a clocking state, thus producingand outputting a DLL clock detection result (or update enable/disablesignals) to the DLL cycle counter 18 and the delay control circuit 13.The DLL clock detection circuit 31 controls the DLL cycle counter 18 tooutput or stop the update clock signal, thus executing or stoppingupdating the delay time by way of the delay circuit 12 and the delaycontrol circuit 13.

The first embodiment is characterized by using the DLL clock detectioncircuit 31 for determining whether or not the DLL clock signal is placedin a clocking state, wherein the DLL clock determination result issupplied to the DLL cycle counter 18 and the delay control circuit 13 soas to stops updating the delay time in a non-clocking state of the DLLclock signal. In the delay-locked control of the DLL circuit of thefirst embodiment, it is possible to prevent the delay time from beingupdated based on the phase detection result which is erroneouslyproduced in the disappearance period of the DLL clock signal. Thus, itis possible to reduce the number of clock pulses adapted to thedelay-locked control and to thereby improve the stability of the DLLcircuit performing the delay-locked control.

The DLL circuit of FIG. 1 is designed to periodically activate the DLLclock detection circuit 31 in response to the DLL clock detection enablesignal output from the DLL cycle counter 18. It can be redesigned tonormally activate the DLL clock detection circuit 31.

2. Second Embodiment

FIG. 2 shows a DLL circuit according to a second embodiment of thepresent invention, which is designed to perform the duty control only,wherein parts identical to those shown in FIGS. 1 and 9 are designatedby the same reference numerals.

In FIG. 2, the initial circuit 11 converts a differential input signal(corresponding to the clock signals CK and /CK) into a clock signal foruse in the DLL circuit. The clock signal output from the initial circuit11 is supplied to the counter clock generation circuit 17 and the dutyadjustment circuit 23.

The counter clock generation circuit 17 divides the frequency of theclock signal so as to generate and output the counter clock signal (seeFIG. 5A) to the DLL cycle counter 18.

The duty detection circuit 21 performs detection as to whether the dutyof the DLL clock signal is above or below 50%. Based on the dutydetection result output from the duty detection circuit 21, the dutycontrol circuit 22 performs the duty control on the update clock signalfrom the DLL cycle counter 18. Based on the duty signal output from theduty control circuit 22, the duty adjustment circuit 23 adjusts the dutyof the clock signal output from the initial circuit 11, thus outputtingthe DLL clock signal.

The DLL cycle counter 18 counts the number of pulses included in thecounter clock signal so as to generate the update clock signal forupdating the duty control. The DLL clock detection circuit 31 detectswhether or not the DLL clock signal disappears (or whether or not theDLL clock signal is placed in a clocking state), thus generating the DLLclock detection result (or the update enable/disable signals) forexecuting or stopping updating the duty control. The details of the DLLclock detection circuit 31 will be described later.

In FIG. 2, the initial circuit 11 converts the differential input signal(corresponding to the clock signals CK and /CK) into the clock signal,which is then supplied to the duty adjustment circuit 23. The dutyadjustment circuit 23 adjusts the duty of the clock signal such that theduty of an internal clock signal (used in the DQ buffer 14) is identicalto or close to 50%, thus generating and outputting the DLL clock signalto the DQ buffer 14.

The DLL clock signal output from the duty adjustment circuit 23 issupplied to the duty detection circuit 21 and subjected to dutydetection. The duty detection result output from the duty detectioncircuit 21 is supplied to the duty control circuit 22. Based on the dutydetection result, the duty control circuit 22 generates the duty signalfor controlling the duty adjustment performed by the duty adjustmentcircuit 23. Based on the duty signal, the duty adjustment circuit 23adjusts the duty of the clock signal output from the initial circuit 11.The details of the duty detection circuit 21 will be described later.

The DLL clock detection circuit 31 receives the DLL clock detectionenable signal (from the DLL cycle counter 18) and the DLL clock signal(from the duty adjustment circuit 23), wherein the DLL clock detectioncircuit 31 is periodically activated by the DLL clock detection enablesignal. The period of the DLL clock detection enable signal is identicalto the update period for updating the duty.

The DLL clock detection circuit 31 detects either a clocking state or anon-clocking state with respect to the DLL clock signal, thus outputtingthe DLL clock detection result (or the update enable/disable signals) tothe DLL cycle counter 18 and the duty detection circuit 21. Thus, theDLL clock detection circuit 31 controls the DLL cycle counter 18 tooutput or stop the update clock signal while also controlling the dutyadjustment circuit 23 to execute or stop the duty control.

The second embodiment is designed such that the DLL clock detectionresult, which is produced by the DLL clock detection circuit 31detecting either the clocking state or the non-clocking state withrespect to the DLL clock signal, is fed back to the duty detectioncircuit 21 for producing the duty detection result, wherein the DLLclock signal is restored by means of the duty detection circuit 21 andthe duty control circuit 22. The constitution and operation of the dutydetection circuit 21 will be described later in detail.

In the delay-locked control of the DLL circuit of the second embodiment,it is possible to prevent the duty from being updated based on the dutydetection result which is erroneously produced in the disappearanceperiod of the DLL clock signal. Thus, it is possible to reduce thenumber of clock pulses adapted to the delay-locked control and tothereby improve the stability of the DLL circuit performing thedelay-locked control. In addition, it is possible to restore the DLLclock signal by means of the duty detection circuit 21 and the dutycontrol circuit 22.

The DLL circuit of FIG. 2 is designed such that the DLL clock detectioncircuit 31 is periodically activated in response to the DLL clockdetection enable signal output from the DLL cycle counter 18. It can beredesigned to normally activate the DLL clock detection circuit 31.

3. Third Embodiment

FIG. 3 shows a DLL circuit according to a third embodiment of thepresent invention, wherein parts identical to those shown in FIGS. 1, 2,and 9 are designated by the same reference numerals. The DLL circuit ofFIG. 3 is designed to perform both the phase control and the dutycontrol, wherein it is a combination of the DLL circuit of FIG. 1achieving the phase control and the DLL circuit of FIG. 2 achieving theduty control.

The duty adjustment circuit 23 adjusts the duty of the clock signal ofthe initial circuit 11 such that the duty of an internal clock signalused in the DQ buffer 14 becomes equal to or close to 50%. The delaycircuit 12 corrects the delay time imparted to the duty-adjusted clocksignal output from the duty adjustment circuit 23 such that the DQoutput signal of the DQ buffer 14 is synchronized with the clock signalsCK and /CK, thus outputting the DLL clock signal to the DQ buffer 14.

The DLL clock signal is supplied to the DQ replica circuit 15 having thesame PVT dependency as the DQ buffer 14. Since the DQ replica circuit 15serves as a buffer circuit having the same dependency of process,voltage, and temperature as the DQ buffer 14, the DQ replica outputsignal is output at the same timing as the DQ output signal. The DQreplica output signal of the DQ replica circuit 15 is supplied to thephase detection circuit 16 and subjected to phase comparison with theclock signals CK and /CK. The phase detection result output from thephase detection circuit 16 is supplied to the delay control circuit 13,thus adjusting the delay time by way of the delay circuit 12.

The DDL clock signal is supplied to the duty detection circuit 21 andsubjected to duty detection, so that the duty detection result issupplied to the duty control circuit 22, thus adjusting the duty by wayof the duty adjustment circuit 23.

The DLL clock detection circuit 31 is periodically activated by the DLLclock detection enable signal, wherein the period of the DLL clockdetection enable signal is identical to the period for updating thedelay time and duty.

The DLL clock detection circuit 31 detects either the clocking state orthe non-clocking state with respect to the DLL clock signal, thusgenerating the DLL clock detection result (or the update enable/disablesignals). The DLL clock detection result is supplied to the delaycontrol circuit 13, the DLL cycle counter 18, and the duty detectioncircuit 21.

In accordance with the DLL clock detection result, the DLL cycle counter18 outputs or stops the update clock signal while the delay controlcircuit 13 executes or stops updating the delay time. In addition, theduty detection circuit 21, the duty control circuit 22, and the dutyadjustment circuit 23 collaborate to execute or stop updating the dutyin accordance with the DLL clock detection result.

The third embodiment is designed such that the DLL clock detectioncircuit 31 detects either the clocking state or the non-clocking statewith respect to the DLL clock signal, and then the DLL clock detectionresult is supplied to the delay control circuit 13, the DLL cyclecounter 18, and the duty control circuit 22, thus inhibiting the delaycontrol and the duty control in the non-clocking state of the DLL clocksignal.

In addition, the third embodiment is designed such that the DLL clockdetection result, which is produced by the DLL clock detection circuit31 detecting either the clocking state or the non-clocking state withrespect to the DLL clock signal, is fed back to the duty detectioncircuit 21 producing the duty detection result, wherein the DLL clocksignal is restored by way of the duty detection circuit 21 and the dutycontrol circuit 22. The constitution and operation of the duty detectioncircuit 21 will be described later in detail.

In the delay-locked control of the DLL circuit of the third embodiment,it is possible to prevent the delay time and the duty from being updatedbased on the phase detection result and the duty detection result whichare erroneously produced in the disappearance period of the DLL clocksignal. Thus, it is possible to reduce the number of clock pulsesadapted to the delay-locked control and to thereby improve the stabilityof the DLL circuit performing the delay-locked control. In addition, itis possible to restore the DLL clock signal by means of the dutydetection circuit 21 and the duty control circuit 22.

The DLL circuit of FIG. 3 is designed such that the DLL clock detectioncircuit 31 is periodically activated in response to the DLL clockdetection enable signal output from the DLL cycle counter 18. It can beredesigned to normally activate the DLL clock detection circuit 31.

FIG. 4 shows the detailed constitution of the DLL clock detectioncircuit 31. The DLL clock detection enable signal from the DLL cyclecounter 18 is supplied to an inverter 101 of the DLL clock detectioncircuit 31.

The output signal of the inverter 101 is supplied to reset terminals Rof D-type latch circuits 105 and 106 (having data terminals D, outputterminals Q, and clock terminals C) as well as a first input terminal“a” of an RS-type latch circuit 104 including NAND circuits 102 and 103.In the RS-type latch circuit 104, the first input terminal “a”corresponds to one input terminal of the NAND circuit 102, and a secondinput terminal “b” corresponds to one input terminal of the NAND circuit103, wherein the NAND circuits 102 and 103 are coupled together suchthat an output terminal “c” of the NAND circuit 102 is connected toanother input terminal of the NAND circuit 103 whose output terminal isconnected to another input terminal of the NAND circuit 102.

The DLL clock detection circuit 31 includes a plurality of D-type latchcircuits wherein the D-type latch circuit 105 is an uppermost one and isfollowed by the D-type latch circuit 106. The date terminal D of thefirst D-type latch circuit 105 is connected to a power-supply voltageVcc (at a high level) while an output terminal Q thereof is connected tothe data terminal D of the second D-type latch circuit 106.

The D-type latch circuits 105 and 106 are followed by a NAND circuit 107having three input terminals a1, a2, and a3 such that the outputterminal Q of the first D-type latch circuit 105 is connected to thefirst input terminal a1 while the output terminal Q of the second D-typelatch circuit 106 is connected to the second input terminal a2. Both theclock terminals C of the D-type latch circuits 105 and 106 receive theDLL clock signal subjected to detection.

FIG. 4 shows the two D-type latch circuits 105 and 106, whereas it ispossible to incorporate three or more D-type latch circuits; hence, theoutput terminal Q of the third D-type latch circuit (not shown) isconnected to the third input terminal a2 of the NAND circuit 107,wherein the data terminal D thereof is connected to the output terminalQ of the second D-type latch circuit 106. Similarly, fourth and otherD-type latch circuits can be incorporated into the DLL clock detectioncircuit 31.

The output signal of the NAND circuit 107 is supplied to the secondinput terminal b of the RS-type latch circuit 104, so that the RS-typelatch circuit 104 outputs an output signal OUT as the DLL clockdetection result (or the update enable/disable signals) toward the delaycontrol circuit 13 and the duty detection circuit 21. The DLL clockdetection result becomes a high-level update enable signal in theclocking state of the DLL clock signal, while it becomes a low-levelupdate disable signal in the non-clocking state of the DLL clock signal.

The DLL clock detection enable signal becomes high so as to activate theDLL clock detection circuit 31, wherein a low-level output signal of theinverter 101 is supplied to the reset terminals R of the D-type latchcircuits 105 and 106 so as to release the reset states of the D-typelatch circuits 105 and 106, so that the output terminals Q of the D-typelatch circuits 105 and 106 are each turned to a low level.

Just after the reset states of the D-type latch circuits 105 and 106 arereleased, the input terminals a1 and a2 of the NAND circuit 107 are eachset at a low level, so that the output signal of the NAND circuit 107 isat a high level which is applied to the second input terminal b of theRS-type latch circuit 104. Since the low-level output signal of theinverter 101 is supplied to the first input terminal a1 (correspondingto one input terminal of the NAND circuit 102), the output terminal c ofthe NAND circuit 102 becomes high, so that the output signal OUT(corresponding to the output terminal of the NAND circuit 103) becomeslow. That is, just after the DLL clock detection circuit 31 isactivated, the RS-type latch circuit 104 outputs the low-level outputsignal OUT serving as the update disable signal declaring thenon-clocking state of the DLL clock signal.

At the leading edge of a first pulse of the DLL clock signal supplied tothe clock terminals C of the D-type latch circuits 105 and 106, theoutput terminal Q of the D-type latch circuit 105 becomes high while theoutput terminal Q of the D-type latch circuit 106 remains low.

When a second pulse of the DLL clock signal is subsequently supplied tothe clock terminals C of the D-type latch circuits 105 and 106, theoutput terminal Q of the D-type latch circuit 106 becomes high while theoutput terminal Q of the D-type latch circuit 105 remains high. That is,every time the D-type latch circuits receive a pulse of the DLL clocksignal, the output terminals Q thereof are sequentially turned to a highlevel in an order from the uppermost one.

When all the output terminals Q of the D-type latch circuits (includingthe D-type latch circuits 105 and 106) become high, all the inputterminals of the NAND circuit 107 become high so that the NAND circuit107 outputs a low-level signal to the second input terminal b of theRS-type latch circuit 104 (corresponding to one input terminal of theNAND circuit 103). Thus, the output terminal of the NAND circuit 103becomes high so that the output signal OUT of the RS-type latch circuit104 correspondingly becomes high, whereby the DLL clock detectioncircuit 31 outputs the update enable signal declaring the clocking stateof the DLL clock signal.

When the DLL clock signal disappears, at least one of the inputterminals a1 to a3 of the NAND circuit 107 remains at a low level sothat the output terminal of the NAND circuit 107 still remains at a highlevel, wherein the output signal OUT of the RS-type latch circuit 104 isnot turned to a high level and still remains at a low level, so that theDLL clock detection circuit 31 outputs the update disable signaldeclaring the non-clocking state of the DLL clock signal.

Thereafter, the DLL clock detection enable signal becomes low, so thatthe RS-type latch circuit 104 retains the previous DLL clock detectionresult (representing either the clocking state or the non-clockingstate) until DLL clock detection enable signal turns to a high level.

The activation period (or high-level period) of the DLL clock detectionenable signal is set to “2×(clock period tCK [ns])” or more when the DLLclock detection circuit 31 uses the two D-type latch circuits 105 and106. In response to the number “n” of D-type latch circuits included inthe DLL clock detection circuit 31 (where n≧3), the activation period ofthe DLL clock detection enable signal is set to “n×(clock period tCK[ns])” or more.

Next, the operation of the DLL clock detection circuit 31 of FIG. 4 willbe described with reference to time charts of FIGS. 5A to 5F.

FIG. 5A shows the counter clock signal, which is generated by thecounter clock generation circuit 17 based on the clock signal of theinitial circuit 11 and supplied to the DLL cycle counter 18.

FIG. 5B shows the DLL clock detection enable signal including pulses C1and C2, which is generated by the DLL cycle counter 18 and is suppliedto the DLL clock detection circuit 31.

FIG. 5C shows a fractional clock signal including pulses B1 and B2, thefrequency of which is a fraction of the frequency of the counter clocksignal subjected to frequency dividing in the DLL cycle counter 18. FIG.5D shows the DLL clock signal output from the delay circuit 12.

FIG. 5E shows the DLL clock detection result produced by the DLL clockdetection circuit 31, wherein the DLL clock detection result becomeshigh to serve as the update enable signal or becomes low to serve as theupdate disable signal. FIG. 5F shows the update clock signal including apulse K1 output from the DLL cycle counter 18.

Next, the operation of the DLL clock detection circuit 31 for detectingeither the clocking state or the non-clocking state and the operation ofthe DLL cycle counter 18 for generating the update clock signal will bedescribed with reference to FIGS. 5A to 5F.

Upon reception of the counter clock signal of FIG. 5A, the DLL cyclecounter 18 counts the number of pulses included in the counter clocksignal so as to generate and output the DLL clock detection enablesignal of FIG. 5B including the pulses C1 and C2, each of which occursin each update period T, to the DLL clock detection circuit 31. The DLLcycle counter 18 also generates a fractional clock signal of FIG. 5Cincluding the pulses B1 and B2, each of which occurs in each updateperiod T. The update clock signal of FIG. 5F is generated based on thefractional clock signal of FIG. 5C including the pulses B1 and B2.

The DLL clock detection circuit 31 starts detecting either the clockingstate or the non-clocking state with respect to the DLL clock signal ofFIG. 5E in response to the pulse C1 shown in FIG. 5B. Since the clockingstate of the DLL clock signal of FIG. 5D occurs in the high-level periodof the pulse C1, the DLL clock detection result becomes high so that theDLL cycle counter 18 generates the pulse K1 of the update clock signalof FIG. 5F. In response to the pulse K1, the delay circuit 12 and thedelay control circuit 13 starts updating the delay time, while the dutycontrol circuit 22 and the duty adjustment circuit 23 starts updatingthe duty.

Due to the non-clocking state of the DLL clock signal occurring at thetiming when the DLL clock detection circuit 31 starts detecting eitherthe clocking state or the non-clocking state of the DLL clock signal inresponse to the pulse C2 of the DLL clock detection enable signal ofFIG. 5B, the DLL clock signal is stacked to a low level so that the DLLclock detection result of FIG. 5E becomes low, wherein the DLL cyclecounter 18 stops generating a pulse of the update clock signal of FIG.5F. In the non-clocking state of the DLL clock signal, the delay circuit12 and the delay control circuit 13 stop updating the delay time, whilethe duty control circuit 22 and the duty adjustment circuit 23 stopupdating the duty.

FIGS. 6A to 6J show waveforms of signals based on simulation of the DLLclock detection circuit 31. Specifically, FIGS. 6A to 6E show thewaveforms of signals in the clocking state of the DLL clock signal,while FIGS. 6F to 6J show the waveforms of signals which are temporarilyvaried due to disappearance of pulses in the DLL clock signal.

The waveforms of signals shown in FIGS. 6A to 6J are drafted inconnection with the DLL clock detection circuit 31 of FIG. 4 includingthe two D-type latch circuits 105 and 106, wherein a high-level periodof a pulse of the DLL clock detection enable signal corresponds to twocycles of pulses of the DLL clock signal.

First, the operation of the DLL circuit in the clocking state of the DLLclock signal will be described with reference to FIGS. 6A to 6E, whereinthe DLL clock detection enable signal of FIG. 6A becomes high at time t1so as to activate the DLL clock detection circuit 31.

The DLL clock detection result of FIG. 6C becomes high time t2 insynchronization with the leading edge of a pulse C1 which is a secondpulse of the DLL clock signal of FIG. 6B counted after time t1 when theDLL clock detection enable signal of FIG. 6A becomes high. At time t3,the update enable/disable signal of FIG. 6D becomes high (declaring theupdate enable state) and is supplied to the delay control circuit 13,the DLL cycle counter 18, and the duty detection circuit 21.

Thus, the update clock signal of FIG. 6E becomes high at time t4 so asto activate the delay control circuit 13 and the duty control circuit22.

In response to the high-level update clock signal from the DLL cyclecounter 18 and the high-level update enable/disable signal from the DLLclock detection circuit 31, the delay control circuit 13 controls thedelay circuit 12 to adjust the delay time applied to the DLL clocksignal.

On the other hand, in response to the high-level update clock signalfrom the DLL cycle counter 18 and the duty detection result from theduty detection circuit 21, the duty control circuit 22 controls the dutyadjustment circuit 23 to adjust the duty of the DLL clock signal, whichis thus set to 50%.

Next, the operation of the DLL circuit coping with the disappearance ofpulses of the DLL clock signal will be described with reference to FIGS.6F to 6J, wherein the DLL clock signal of FIG. 6G is normally placed inthe clocking state before time t1 so that both the DLL clock detectionresult of FIG. 6H and the update enable/disable signal of FIG. 6I are ata high level.

At time t1 when the DLL clock detection enable signal of FIG. 6F becomeshigh, the DLL clock detection circuit 31 starts detecting either theclocking state or the non-clocking state of the DLL clock signal.

At time t1, pulses disappear in the DLL clock signal of FIG. 6G, whichis stacked to a high level.

Thus, the DLL clock detection result of FIG. 6H becomes low at time t1,and then the update enable/disable signal of FIG. 6I becomes low(declaring the update disable state) at time t3. That is, the updatedisable signal is supplied to the delay control circuit 13, the DLLcycle counter 18, and the duty detection circuit 21.

Thus, the DLL cycle counter 18 does not generate a pulse of the updateclock signal shown in FIG. 6J, thus stopping updating the delay controlcircuit 13 and the duty detection circuit 21. Therefore, the dutydetection circuit 21 and the duty control circuit 22 stop updating theduty of the DLL clock signal, while the delay circuit 12 and the delaycontrol circuit 13 stop updating the delay time applied to the DLL clocksignal. For this reason, the previous duty and the previous delay timeare maintained with respect to the DLL clock signal.

FIG. 7 shows the detailed constitution of the delay control circuit 13,which is designed to determine the delay time of the delay circuit 12based on the phase detection result produced by the phase detectioncircuit 16.

As shown in FIG. 7, the delay control circuit 13 is constituted of anadder 201, D-type latch circuits 202, 203, and 204 (having dataterminals D, output terminals Q, and clock terminals C), and an ANDcircuit 205. All the output terminals Q of the D-type latch circuits202, 203, and 204 are connected to the adder 201, which also receivesthe phase detection result (representing a count-up signal UP and acount-down signal DOWN) output from the phase detection circuit 16. Theadder 201 outputs three output signals to the date terminals D of theD-type latch circuits 202, 203, and 204 respectively.

A first input terminal of the AND circuit 205 receives the update clocksignal from the DLL cycle counter 18, while a second input terminalthereof receives the DLL clock detection result (i.e. the updateenable/disable signals) from the DLL clock detection circuit 31. Theoutput terminal of the AND circuit 205 is connected to the clockterminals C of the D-type latch circuits 202, 203, and 204 respectively.

In the delay control circuit 13 of FIG. 7, the D-type latch circuits202, 203, and 204 latch respective delay times, which are supplied tothe adder 201. Upon reception the phase detection signal (representingeither the counter-up signal UP or the count-down signal DOWN), theadder 201 update the present delay time by increasing or decreasing.

When the DLL clock detection result becomes high (denoting the updateenable signal) during the high-level period of the update clock signal,the output signal of the adder 201 (representing the updated delay time)is latched by the D-type latch circuits 202 to 204, from which it issupplied to the delay circuit 12.

When the DLL clock detection result becomes low (denoting the updatedisable signal) during the high-level period of the update clock signal,the output signal of the AND circuit 205 becomes low so that the updateddelay time of the adder 201 is not latched by the D-type latch circuits202 to 204. At this time, the D-type latch circuits 202 to 204 are notupdated so as to still retain the previous delay time.

FIG. 7 shows the three D-type latch circuits 202 to 204, whereas thenumber of D-type latch circuits included in the delay control circuit 13can be increased to four or more as necessary.

Next, the detailed constitution and operation of the duty detectioncircuit 21 will be described with reference to FIGS. 8A to 8C. The dutydetection circuit 21 is designed to detect the duty of the DLL clocksignal compared to the reference duty ratio of 50%.

In the duty detection circuit 21 of FIG. 8A, an inverter 301 receivesthe DLL clock detection result (i.e. the update enable/disable signals)from the DLL clock detection circuit 31 so as to provide an outputsignal thereof to an inverter 302 and an ON/OFF control terminal S of aselector 306.

Meanwhile, the DLL clock signal is supplied to a duty detector 303 and adata terminal D of a D-type latch circuit 304. The output signal of theduty detector 303 is supplied to a first input terminal “a” of theselector 306. The output signal of the D-type latch circuit 304 at itsoutput terminal Q is inverted in logic level by an inverter 305 and isthen supplied to a second input terminal “b” of the selector 306.

The duty detector 303 detects whether the duty (i.e. the high-levelperiod of a pulse of the DLL clock signal) is greater or less than 50%,thus producing the duty detection result. In the case of FIG. 8B inwhich the duty is greater than 50%, the duty detector 303 outputs a dutydecrease signal (i.e. a low-level signal) to the first input terminal“a” of the selector 306. In the case of FIG. 8C in which the duty isless than 50%, the duty detector 303 outputs a duty increase signal(i.e. a high-level signal) to the first input terminal “a” of theselector 306.

In response to the high-level DLL clock detection result (declaring theclocking state of the DLL clock signal), the selector 306 switches overto the first input terminal “a” so as to select the duty detectionresult of the duty detector 303, which is then output to the dutycontrol circuit 22.

In response to the low-level DLL clock detection result (declaring thenon-clocking state of the DLL clock signal), the selector 306 switchesover to the second input terminal “b” so as to select the output signalof the inverter 305, which is then output to the duty control circuit22.

In the transition of the DLL clock detection result to the low level,the D-type latch circuit 304 latches the stack level of the DLL clocksignal, which is inverted by the inverter 305 (whose input terminal isconnected to the output terminal Q of the D-type latch circuit 304) andis then supplied to the second input terminal b of the selector 306.

When the DLL clock detection result declares the non-clocking state ofthe DLL clock signal, the duty detection result turns to a low level(representing the duty decrease signal) in response to the “high” levelstacked in the DLL clock signal, while the duty detection result turnsto a high level (representing the duty increase signal) in response tothe “low” level stacked in the DLL clock signal. Responding to the highlevel or the low level of the duty detection result, the duty of the DLLclock signal is restored by increasing or decreasing. This makes itpossible to control the duty of the DLL clock signal, thus restoring theclocking state of the DLL clock signal.

Lastly, it is apparent that the present invention is not limited to theabove embodiments, but may be modified and changed without departingfrom the scope and spirit of the invention.

What is claimed is:
 1. A DLL circuit adjusting a duty of an input clocksignal, comprising: a duty control circuit that produces a duty signalto control the duty of the input clock signal; a duty adjustment circuitthat adjusts the duty of the input clock signal based on the dutysignal, thus producing a DLL clock signal; and a DLL clock detectioncircuit that detects either a clocking state or a non-clocking statewith respect to the DLL clock signal, wherein the DLL clock detectioncircuit controls the duty control circuit to produce the duty signal tochange the DLL clock signal from the non-clocking state to the clockingstate when the DLL clock detection circuit detects the non-clockingstate with respect to the DLL clock signal.
 2. A DLL circuit comprising:a duty control circuit that produces a duty signal to control a duty ofa first clock signal input thereto; a duty adjustment circuit thatadjusts the duty of the first clock signal based on the duty signal,thus producing a second clock signal; a delay control circuit thatproduces a delay signal to control a delay time applied to the secondclock signal; a delay circuit that applies the delay time to the secondclock signal based on the delay signal, thus producing a DLL clocksignal; and a DLL clock detection circuit that detects either a clockingstate or a non-clocking state with respect to the DLL clock signal,wherein the DLL clock detection circuit controls at least one of theduty control circuit and the delay control to produce corresponding oneor ones of the duty signal and the delay signal to change the DLL clocksignal from the non-clocking state to the clocking state when the DLLclock detection circuit detects the non-clocking state of the DLL clocksignal.
 3. A DLL circuit adjusting a phase of an input clock signal,comprising: a delay control circuit that produces a delay signal tocontrol a delay time applied to the input clock signal; a delay circuitthat applies the delay time to the input clock signal based on the delaysignal, thus producing a DLL clock signal; and a DLL clock detectioncircuit that detects either a clocking state or a non-clocking statewith respect to the DLL clock signal, wherein the DLL clock detectioncircuit controls the delay control circuit to produce the delay signalto change the DLL clock signal from the non-clocking state to theclocking state when the DLL clock detection circuit detects thenon-clocking state with respect to the DLL clock signal, and wherein theDLL clock signal and a DLL clock detection enable signal forperiodically activating the DLL clock detection circuit are supplied tothe DLL clock detection circuit, which includes a counter for counting anumber of pulses included in the DLL clock signal during activation ofthe DLL clock detection enable signal, and a latch circuit for declaringthe clocking state of the DLL clock signal when the counted number isgreater than a prescribed number and for declaring the non-clockingstate of the DLL clock signal when the counted number is less than theprescribed number.
 4. The DLL circuit according to claim 1, wherein theDLL clock signal and a DLL clock detection enable signal forperiodically activating the DLL clock detection circuit are supplied tothe DLL clock detection circuit, which includes a counter for counting anumber of pulses included in the DLL clock signal during activation ofthe DLL clock detection enable signal, and a latch circuit for declaringthe clocking state of the DLL clock signal when the counted number isgreater than a prescribed number and for declaring the non-clockingstate of the DLL clock signal when the counted number is less than theprescribed number.
 5. A DLL circuit adjusting a phase of an input clocksignal, comprising: a delay control circuit that produces a delay signalto control a delay time applied to the input clock signal; a delaycircuit that applies the delay time to the input clock signal based onthe delay signal, thus producing a DLL clock signal; a DLL clockdetection circuit that detects either a clocking state or a non-clockingstate with respect to the DLL clock signal; a DQ buffer for bufferingthe DLL clock signal; a DQ replica circuit for receiving the DLL clocksignal so as to output a DQ replica output signal; and a phase detectioncircuit for detecting a phase difference between the input clock signaland the DQ replica output signal, thus producing a phase detectionresult, wherein the DLL clock detection circuit controls the delaycontrol circuit to produce the delay signal to change the DLL clocksignal from the non-clocking state to the clocking state when the DLLclock detection circuit detects the non-clocking state with respect tothe DLL clock signal, wherein the delay control circuit includes a latchcircuit for latching the delay time presently applied to the DLL clocksignal, and an adder for adding the phase difference to the delay timebased on the phase detection result so as to produce an addition result,and wherein the addition result of the adder is latched by the latchcircuit as a new delay time when the DLL clock detection circuitdeclares the clocking state of the DLL clock signal.
 6. The DLL circuitaccording to claim 1 further comprising a duty detection circuitincluding a duty detector for detecting the duty of the DLL clocksignal, a latch circuit for latching a stacked level of the DLL clocksignal, and a selector for selecting an output signal of the dutydetector when the DLL clock detection circuit declares the non-clockingstate of the DLL clock signal and for selecting the stacked level or itsinverted level when the DLL clock detection circuit declares thenon-clocking state of the DLL clock signal.
 7. A semiconductor deviceincluding the DLL circuit according to claim
 1. 8. A semiconductordevice comprising: a control circuit that responds to first and secondfeedback signals to produce a control signal; and a DLL clock signalgeneration circuit that receives an input clock signal and the controlsignal and generates a DLL clock signal that is related to the inputclock signal and controlled in at least one of a phase and a duty inresponse to the control signal, wherein the first feedback signal isproduced in response to at least the DLL clock signal and the secondfeedback signal that is produced in response to the DLL clock signalunchanged in a logic level during at least one cycle of the input clocksignal.
 9. The semiconductor device according to claim 8, wherein theDLL clock signal generation circuit comprises a duty adjustment circuit,and wherein the control circuit comprises a duty control circuit that iscoupled to receive the first and second feedback signals and suppliesthe control signal to the duty adjustment circuit to adjust a duty ofthe DLL clock signal.
 10. The semiconductor device according to claim 9,wherein the DLL clock signal generation circuit further comprises adelay circuit coupled in series with the duty adjustment circuit,wherein the control circuit further comprises a delay control circuitthat produces an additional control signal in response to the first andsecond feedback signals, and wherein the additional control signal issupplied to the delay circuit to delay the DLL clock signal with respectto the input clock signal.
 11. The semiconductor device according toclaim 10, wherein the first feedback signal is produced in response tothe input clock signal.
 12. the semiconductor device according to claim8, wherein the DLL clock signal generation circuit comprises a delaycircuit, wherein the control circuit comprises a delay control circuit,wherein the first feedback signal is produced in response to the inputclock signal and the DLL clock signal, and wherein the delay controlcircuit is coupled to receive the first and second feedback signals andsupplies the control signal to the delay circuit to delay the DLL clocksignal with respect to the input clock signal.
 13. The semiconductordevice according to claim 12, wherein the DLL clock signal generationcircuit further comprises a duty adjustment circuit coupled in serieswith the delay circuit, wherein the control circuit further comprises aduty control circuit that produces an additional control signal inresponse to the DLL clock signal and the second feedback signal, andwherein the additional control signal is supplied to the duty adjustmentcircuit to control a duty of the DLL clock signal.
 14. A delay lockedloop (DLL) circuit comprising: a delay control circuit that produces adelay signal to control a delay time applied to an input clock signal; adelay circuit that applies the delay time to the input clock signalbased on the delay signal, thus producing a DLL clock signal; and aclock detection circuit that detects either a clocking state or anon-clocking state with respect to a clock signal based on the inputclock signal, wherein the clock detection circuit controls the delaycontrol circuit to prevent updates to the delay signal when thenon-clocking state is detected and to allow updates to the delay signalwhen the clocking state is detected.
 15. The DLL circuit of claim 14,wherein the clock signal based on the input clock signal is the DLLclock signal.
 16. The DLL circuit of claim 14, wherein the clockdetection circuit comprises a plurality of D-type latches, a first latchamong the plurality of D-type latches having an output terminalconnected to an input terminal of a second latch among the plurality ofD-type latches.
 17. The DLL circuit of claim 16, wherein the clockdetection circuit allows updates to the delay signal when the pluralityof D-type latches each have the same logic level on respective outputterminals.
 18. The DLL circuit of claim 14, further comprising a dutycontrol circuit and a duty adjustment circuit to adjust the duty of theDLL clock signal.
 19. The DLL circuit of claim 18, wherein the dutycontrol circuit controls the duty adjustment circuit to adjust the dutyof the DLL clock signal to approximately 50%.
 20. The DLL circuit ofclaim 18, wherein the clock detection circuit controls the duty controlcircuit to prevent adjustment of the duty of the DLL clock signal whenthe non-clocking state is detected and to allow adjustment of the dutyof the DLL clock signal when the clocking state is detected.